(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly relates to field effect transistors having sub-quarter micrometer channel lengths and improved short channel effect characteristics.
(2) Description of the Prior Art
Dramatic increases in circuit density and circuit performance have occurred in recent years in the semi-conductor industry. These increases are largely due to the reduction in size of the discrete device that make up the circuits. The Field Effect Transistor (FET) having a silicon gate electrode and self-aligned source/drain contact areas is currently the device of choice for Ultra Large Scale Integration (ULSI) because of their very small size, high packing density, low power consumption and high yields.
Conventional FETs are typically fabricated by patterning polysilicon gate electrodes on a single crystal semiconductor substrate having a thin gate oxide therebetween. The gate electrode structure is used as a diffusion barrier mask to form self-aligned source/drain areas in the substrate adjacent to the sides of the gate electrode. The distance from the source junction to drain junction under the gate electrode is defined as the channel length of the FET.
The reduction in size of the FET and their high packing density on the semiconductor substrate is mainly due to advances in the semiconductor technologies, such as high resolution photolithographic techniques and anisotropic plasma etching, to name a few. For example, FETs are currently used in the industry having channel lengths that are less than a half micrometer (0.5 um) in length. If further increases in packing density and increase in device performance are to continue, then it is necessary to further reduce the device size and more particularly, the channel length to sub-quarter micrometer dimensions (that is to less than 0.25 um). However, as this down scaling in device size continues and the channel length is reduced the FET experiences a number of undesirable electrical characteristic known as short channel effects (SCE). These short channel effects become more severe as the device physical dimensions are scaled. This result is due to the fact that the band gap and built in potential at junctions are an intrinsic constant of crystalline material.
These adverse short channel effects result from the electric field distribution in the channel area when the integrated circuit is powered up, which lead to a number of problems. For example, electrons ejected from the drain can acquire sufficient energy to be injected into the gate oxide resulting in charge build up in the gate oxide that causes threshold voltage shifts. Unfortunately, this hot electron effect can degrade device performance after the product is in use (in the field). Another adverse effect is the threshold voltage lowering referred to as threshold voltage roll-off, in which the threshold voltage (V.sub.th) decreases with decreasing channel length and occurs when the channel length is comparable to the source/drain diffusion depth, a result of reduction of stored charge under the gate region.
To minimize the short channel effects, it is common practice in the semiconductor industry to fabricate FET structures with double diffused drains (DDD) or Lightly Doped Drains (LDD). These DDD of LDD FET structures, having drains with low dopant concentration adjacent to the gate electrodes, modify the electric fields at the drain so as to minimize or eliminate the hot electron and roll-off effects. Method for reducing the junction depth of the source/drain also reduce threshold voltage roll-off.
Another problem occurring with the conventional FET, having a patterned gate electrode, is the inability with the current photolithography techniques to repeatedly and reliably produce sub-quarter micrometer (&lt;0.25 um) wide gate electrode structures.
The reverse self-aligned field effect transistor process as been suggested as an alternative to conventional FETs for forming sub-micrometer gate electrode structures. For example, methods of forming this alternate FET structure are described by W. J. Boardman, et al U.S. Pat. No. 5,196,357 and by N. Tsai, U.S. Pat. No. 5,071,780. A related FET structure entitled "A Sub-0.1-um Grooved Gate MOSFET with High Immunity to Short-Channel Effects", is described by J. Tanaka et al in the IEDM Proceedings of the IEEE, 1993 pages 537-540.
In these reverse self-aligned FET structures a multilayer, having a conducting layer, such as polysilicon, as one of the layers is deposited over the device areas where the FETs are to be built. Openings having vertical sidewalls are etched in the multilayer at locations where the FET gate electrodes are to be formed. A gate oxide and sidewall insulating layers are formed in the opening and a second conducting layer is then deposited and patterned to form the self-aligned overlapping gate electrode. The patterned multilayer and out diffusion of dopant impurities therefrom and into the substrate, serves as the source/drain areas of the FET. However, a number of problem still occur that make manufacturing these FETs difficult, such as forming low resistance contacts to the source/drain areas of the FET and the ability to fabricate shallow source/drain junctions.
There is still, therefore, a strong need in the semiconductor industry for a more controllable and cost effective manufacturing process for forming reverse self-aligned field effect transistor having immunity from short channel effects.